(1) Field of the Invention
The present invention relates to the field of layout verification for an integrated circuit description. The integrated circuit description typically includes a listing of cell elements and interconnections there between and is stored as data within one or more computer readable memory units of a computer system.
(2) Prior Art
Many custom designed integrated circuits (IC), e.g., application specific integrated circuits (ASICs) or other custom IC circuits, are designed and fabricated using a number of various computer implemented automatic design processes. Within these processes, a high level design language description of the integrated circuit (e.g., HDL, VHDL, Verilog, etc.) can be translated by a computer system into a netlist of generic logic. The generic logic can then be translated into a netlist of technology specific gates and interconnections there between that represent the IC design. The netlist more specifically is a listing of circuit elements and their connectivity and is stored within computer memory units of a computer system.
The cells of the netlist are then placed spatially in an integrated circuit layout by a computer implemented placer and the connections between the cells are then routed through the appropriate areas of the layout by a computer implemented router. After place and route, the IC design is represented by specific geometries (e.g., transistors) and interconnections between the geometries. Once the IC design has been placed and routed, circuit designers run a battery of tests on the result to verify that the IC design meets specific design rules and matches logically with the schematic design. These tests are performed by a computer system in a process called layout verification. Layout verification is very important because it is one of the last tests performed before the integrated circuit design is committed to silicon.
The netlist containing the geometries and connectivity that is input to the layout verification processes is generally represented as hierarchical block of subdesigns with each individual subdesign comprising different parts of the integrated circuit. FIG. 1 illustrates one exemplary integrated circuit design 10 having four subcell designs (or subdesigns): B 14; C 20; D 16; and E 18. The top level, design A 12, includes in its description each subcell design (e.g., 14, 16, 18, 20) plus any local structures 22 which are included directly within the top level 12. Each of the subcell designs can also include, like the top level 12, other subcell designs and so on. Under this representation, each subcell design has one parent design and can have one or more child designs. Those subcell designs located at the bottom of the hierarchy are leaf cell designs and contain only the data (e.g., geometry and connectivity) that needs to be layout verified.
The subcell designs of a netlist 10 are typically represented as different files within a computer system's disk access unit (e.g., a disk drive). Therefore, a netlist that requires layout verification is stored as a multi-file database. For instance, the actual file representation of design A 12 can be a directory having descriptions of the local structures 22 stored therein and having disk references to the files that contain the information for subcell design B 14, subcell design C 20, subcell design D 16 and subcell design E 18. This data is transferred in streams within the computer system using a well known graphic design stream format (e.g., GDSII format). In the GDSII format, the parent-child representations of the subcell designs are maintained as the data is passed within the computer system and to the layout verification process.
In the past, integrated circuit designs 10 were passed through the layout verification process in their entirety using either a hierarchical layout verification process or using a flattened layout verification process. In the hierarchical layout verification process, all of the disk files that represent the subcell designs (e.g., 14-20) of the top level design 12 and the subdesigns of the subcell designs (14-20), etc., are passed through the layout verification process for design rule checking (DRC) and layout versus schematic (LVS) comparison. In hierarchical fashion, the data from the disk unit is processed in accordance with its position within the hierarchical tree of the IC design. During layout verification, several disk directories are read to obtain the entire netlist data. This is done on each file of the IC design 10 every time verification is required.
In flattened layout verification, all of the files representing the leaf cells of the design 10 are incorporated (merged) directly into the top level 12 design. Further, any local structure stored in any subcell is also merged upward into the root file 12. That is to say, all leaf cells are pushed into a single disk directory to form one large file in the GDSII format that contains only geometry and connectivity information. This, like the hierarchical method, requires that all disk files be processed for layout verification. This entirely flattened top level design 12, or file, is then passed through layout verification for design rule checking (DRC) and layout versus schematic (LVS) comparison.
Therefore, in both cases, hierarchical or flattened layout verification, the input to the layout verification process is the entire integrated circuit design 10 for each instance that verification is required. This is true even if only a small part of the IC design 10 had been modified since the last layout verification process was run.
The prior art method of layout verification over the entire chip design requires about 10 or 20 minutes to complete for relatively small circuit designs. However, over the past 10 years, circuit designs have been growing increasingly larger thereby requiring more layout verification processing time. Today, IC chip designs are routinely in the 20-40 million transistors. At these chip sizes, the prior art method of layout verification, that requires the entire IC design as input for each verification, is consuming about four to five hours of processing time per integrated circuit chip design. This long verification period is required each time the integrated circuit design is modified for any reason or to any extent. Therefore, the prior art layout verification procedure is very inefficient. It would be advantageous to provide a layout verification process that can operate more effectively on an integrated circuit design to reduce the layout verification processing period required to verify the IC design.
Accordingly, the present invention provides a layout verification process that operates efficiently on an integrated circuit design to reduce the layout verification process period required of a circuit designer. Further, the present invention provides such an efficient layout verification method that includes design rule checking and layout versus schematic verification. Moreover, the present invention provides a particularly efficient layout verification method for integrated circuit designs that are passed through a layout verification process for the second and subsequent times. These and other advantages of the present invention not specifically described above will become clear within discussions of the present invention herein.